start of a 4004 emulator
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3mu/Intel4004.c
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184
3mu/Intel4004.c
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/* Intel 4004 emulator. 2024, DTB. Incomplete.
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* I didn't know anything about the i4004 before starting to write this file. I
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* know slightly more now. */
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/* Name - Bits 11_10__9__8__7__6__5__4__3__2__1__0
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* Bit - 1 | | | bit -> ||
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* Nybble - 4 | | nybble -> |_________|
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* Byte - 8 | byte -> |_____________________|
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* Word - 12 word -> |_________________________________| */
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/* 24---------------------|
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*
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* words 12---------|12---------|
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* bytes 8------|8------|8------|
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* nybbles 4--|4--|4--|4--|4--|4--|
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* bits 111111111111111111111111 */
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#if __STDC_VERSION__ >= 199901L
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/* C99 type definitions */
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# include <stdint.h>
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typedef _Bool Bit;
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typedef uint8_t Nybble;
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typedef uint8_t Byte;
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typedef uint16_t Word;
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#else
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/* C89 type definitions - probably fine but may need per-platform tweaks. */
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/* Must fit at least 1 bit. */ typedef unsigned char Bit;
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/* Must fit at least 4 bits. */ typedef unsigned char Nybble;
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/* Must fit at least 8 bits. */ typedef unsigned char Byte;
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/* Must fit at least 12 bits. */ typedef unsigned int Word;
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#endif
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#define LOW_NYBBLE(b) ((b) & 0x0F) /* 0b 0000 1111 */
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#define HIGH_NYBBLE(b) ((b) & 0xF0) /* 0b 1111 0000 */
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/* Intel 4004 datasheet */
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/* <https://datasheets.chipdb.org/Intel/MCS-4/datashts/intel-4004.pdf> */
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struct Intel4004_State {
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Bit carry;
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Bit test; /* A pin on the chip. */
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Nybble acc; /* Accumulator */
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Nybble reg[16]; /* R0 through RF */
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Word pc[4]; /* PC0 through PC3 */
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Byte *rom;
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Byte *ram;
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};
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/* Intel 4004 instruction set */
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/* <http://e4004.szyc.org/iset.html> */
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enum Intel4004_Instruction {
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/* Summary Mnemonic Hex Binary opcode */
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/* No-op */ NOP = 0x0, /* 0b 0000 0000 */
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/* INVALID 0b 0000 0001 through 0b 0000 1111 */
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/* Jump conditional */ JCN = 0x10, /* 0b 0001 CCCC */
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/* Fetch immediate */ FIM = 0x20, /* 0b 0010 RRR0 */
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/* Send register control */ SRC = 0x21, /* 0b 0010 RRR1 */
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/* Fetch indirect */ FIN = 0x30, /* 0b 0011 RRR0 */
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/* Jump indirect */ JIN = 0x31, /* 0b 0011 RRR1 */
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/* Jump unconditional */ JUN = 0x40, /* 0b 0100 AAAA */
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/* Jump to subroutine */ JMS = 0x50, /* 0b 0101 AAAA */
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/* Increment */ INC = 0x60, /* 0b 0110 RRRR */
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/* Increment and skip */ ISZ = 0x70, /* 0b 0111 RRRR */
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/* Add */ ADD = 0x80, /* 0b 1000 RRRR */
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/* Subtract */ SUB = 0x90, /* 0b 1001 RRRR */
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/* Load */ LD = 0xA0, /* 0b 1010 RRRR */
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/* Exchange */ XCH = 0xB0, /* 0b 1011 RRRR */
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/* Branch back and load */ BBL = 0xC0, /* 0b 1100 DDDD */
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/* Load immediate */ LDM = 0xD0, /* 0b 1101 DDDD */
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/* Write main memory */ WRM = 0xE0, /* 0b 1110 0000 */
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/* Write RAM port */ WMP = 0xE1, /* 0b 1110 0001 */
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/* Write ROM port */ WRR = 0xE2, /* 0b 1110 0010 */
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/* INVALID 0xE3 0b 1110 0011 */
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/* Write status char 0 */ WR0 = 0xE4, /* 0b 1110 0100 */
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/* Write status char 1 */ WR1 = 0xE5, /* 0b 1110 0101 */
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/* Write status char 2 */ WR2 = 0xE6, /* 0b 1110 0110 */
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/* Write status char 3 */ WR3 = 0xE7, /* 0b 1110 0111 */
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/* Subtract main memory */ SBM = 0xE8, /* 0b 1110 1000 */
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/* Read main memory */ RDM = 0xE9, /* 0b 1110 1001 */
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/* Read ROM port */ RDR = 0xEA, /* 0b 1110 1010 */
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/* Add main memory */ ADM = 0xEB, /* 0b 1110 1011 */
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/* Read status char 0 */ RD0 = 0xEC, /* 0b 1110 1100 */
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/* Read status char 1 */ RD1 = 0xED, /* 0b 1110 1101 */
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/* Read status char 2 */ RD2 = 0xEE, /* 0b 1110 1110 */
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/* Read status char 3 */ RD3 = 0xEF, /* 0b 1110 1111 */
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/* Clear both */ CLB = 0xF0, /* 0b 1111 0000 */
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/* Clear carry */ CLC = 0xF1, /* 0b 1111 0001 */
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/* Increment accumulator */ IAC = 0xF2, /* 0b 1111 0010 */
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/* Complement carry */ CMC = 0xF3, /* 0b 1111 0011 */
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/* Complement */ CMA = 0xF4, /* 0b 1111 0100 */
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/* Rotate left */ RAL = 0xF5, /* 0b 1111 0101 */
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/* Rotate right */ RAR = 0xF6, /* 0b 1111 0110 */
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/* Transfer carry and clear */ TCC = 0xF7, /* 0b 1111 0111 */
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/* Decrement accumulator */ DAC = 0xF8, /* 0b 1111 1000 */
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/* Transfer carry subtract */ TCS = 0xF9, /* 0b 1111 1001 */
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/* Set carry */ STC = 0xFA, /* 0b 1111 1010 */
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/* Decimal adjust accumulator */ DAA = 0xFB, /* 0b 1111 1011 */
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/* Keyboard process */ KBP = 0xFC, /* 0b 1111 1100 */
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/* Designate command line */ DCL = 0xFD /* 0b 1111 1101 */
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/* INVALID 0xFE 0b 1111 1110 */
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/* INVALID 0xFF 0b 1111 1111 */
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};
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/* Does nothing. */
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void Intel4004_NOP(struct Intel4004_State *state){ /* 0b 0000 0000 */
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++*state->pc;
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return;
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}
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#define INTEL4004_JCN_COND_INVERT 0x01 /* 0b 0000 0001 */
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#define INTEL4004_JCN_COND_ACCZERO 0x02 /* 0b 0000 0010 */
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#define INTEL4004_JCN_COND_CARRYON 0x04 /* 0b 0000 0100 */
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#define INTEL4004_JCN_COND_TESTON 0x08 /* 0b 0000 1000 */
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#define INTEL4004_JCN_COND_ISINVERT(b) ((b) & INTEL4004_JCN_COND_INVERT)
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#define INTEL4004_JCN_COND_ISACCZERO(b) ((b) & INTEL4004_JCN_COND_ACCZERO)
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#define INTEL4004_JCN_COND_ISCARRYON(b) ((b) & INTEL4004_JCN_COND_CARRYON)
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#define INTEL4004_JCN_COND_ISTESTON(b) ((b) & INTEL4004_JCN_COND_TESTON)
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/* Jumps conditionally to the address in the following byte.
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* If *state->pc & 0x01, the condition is inverted.
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* If *state->pc & 0x02, a zero accumulator satisfies the condition.
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* If *state->pc & 0x04, a one carry flag satisfies the condition.
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* If *state->pc & 0x08, a one test flag satisfies the condition. */
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void Intel4004_JCN(struct Intel4004_State *state){ /* 0b 0001 CCCC */
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*state->pc =
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!INTEL4004_JCN_COND_ISINVERT(state->rom[*state->pc])
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&& ( (INTEL4004_JCN_COND_ISACCZERO(state->rom[*state->pc])
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&& state->acc == 0)
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|| (INTEL4004_JCN_COND_ISCARRYON(state->rom[*state->pc])
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&& state->carry == 1)
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|| (INTEL4004_JCN_COND_ISTESTON(state->rom[*state->pc])
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&& state->test == 1))
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? state->rom[*state->pc + 1]
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: *state->pc + 2;
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return;
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}
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/* Macros to get the register pair from FIM, SRC, FIN, and JIN.
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* INTEL4004_REGPAIR(opcode) returns the first register, the second register is
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* the increment.
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* High nybbles tend to be stored in the first register and low nybbles in the
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* second. */
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#define INTEL4004_REGPAIR_BYTEMASK 0x0E /* 0b 0000 1110 */
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#define INTEL4004_REGPAIR(b) ((b) & INTEL4004_REGPAIR_BYTEMASK)
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/* Fetches an immediate byte from ROM. */
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void Intel4004_FIM(struct Intel4004_State *state){ /* 0b 0010 RRR0 */
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state->reg[INTEL4004_REGPAIR(state->rom[*state->pc])]
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= HIGH_NYBBLE(state->rom[*state->pc + 1]);
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state->reg[INTEL4004_REGPAIR(state->rom[*state->pc]) + 1]
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= LOW_NYBBLE(state->rom[*state->pc + 1]);
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*state->pc += 2;
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return;
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}
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void Intel4004_SRC(struct Intel4004_State *state){ /* 0b 0010 RRR1 */
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}
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void Intel4004_FIN(struct Intel4004_State *state){ /* 0b 0011 RRR0 */
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}
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